Issue It is unclear to me how the compiler will automatically know to compile for 64-bit when it needs to. How does it know when it can confidently target 32-bit? I am mainly curious about how the compiler knows which
Continue readingTag: cpu-architecture
[SOLVED] How does perf record (or other profilers) pick which instruction to count as costing time?
Issue Recently, I found out that actually perf (or pprof) may show in disassembly view instruction timing near the line that didn’t actually take this time. The real instruction, which actually took this time, is before it. I know a
Continue reading[SOLVED] Is a schedulable unit of CPU time slice process or thread?
Issue I want to clarify whether "a schedulable unit of CPU time slice" is "process" or "thread" (kernel managed thread). What I mean by "schedulable unit of CPU time slice" is the unit which CPU scheduler of an operating system
Continue reading[SOLVED] How are functions encoded/stored in memory?
Issue I understand how things like numbers and letters are encoded in binary, and thus can be stored as 0’s and 1’s. But how are functions stored in memory? I don’t see how they could be stored as 0’s and
Continue reading[SOLVED] Bad CPU type in executable mac Intel core
Issue Trying to install a specific version of nvm But I get nvm install 16.14.2 -bash: /opt/homebrew/bin/awk: Bad CPU type in executable -bash: /opt/homebrew/bin/awk: Bad CPU type in executable -bash: /opt/homebrew/bin/awk: Bad CPU type in executable -bash: /opt/homebrew/bin/awk: Bad CPU
Continue reading[SOLVED] Why is the page size of Linux (x86) 4 KB, how is that calculated?
Issue The default memory page size of the Linux kernel on x86 architecture was 4 KB, I wonder how was that calculated, and why ? Solution The default page size is fixed by what the MMU (memory management unit) of
Continue reading[SOLVED] Latency bounds and throughput bounds for processors for operations that must occur in sequence
Issue My textbook (Computer Systems: A programmer’s perspective) states that a latency bound is encountered when a series of operations must be performed in strict sequence, while a throughput bound characterizes the raw computing capacity of the processor’s functional units.
Continue reading[SOLVED] How does a pipelined processor handle excessively unrolled loops?
Issue Suppose for (int i = 0; i < N; ++i) { sum += nums[i]; } is unrolled by the compiler to something that looks like for (int i = 0; i < N; i += 4) { sum1 +=
Continue reading[SOLVED] How does a pipelined processor handle excessively unrolled loops?
Issue Suppose for (int i = 0; i < N; ++i) { sum += nums[i]; } is unrolled by the compiler to something that looks like for (int i = 0; i < N; i += 4) { sum1 +=
Continue reading[SOLVED] Can x86's MOV really be "free"? Why can't I reproduce this at all?
Issue I keep seeing people claim that the MOV instruction can be free in x86, because of register renaming. For the life of me, I can’t verify this in a single test case. Every test case I try debunks it.
Continue reading