[SOLVED] Which constructs in Verilog can contain function definition?

Issue

I am new to verilog and trying to figure out where the function can be defined/declared in verilog (like I know function can be defined in packages, what else?). Thanks in advance.

Solution

In Verilog, a function can be declared between

  • module and endmodule (ie in the current region of a module – inside a module, but outside an initial or always block)
  • generate and endgenerate

That’s it.

In System-Verilog, a function can be declared between

  • module and endmodule
  • generate and endgenerate

and

  • class and endclass
  • interface and endinterface
  • checker and endchecker
  • package and endpackage
  • program and endprogram

and

  • outside a module / interface / checker / package / program

Answered By – Matthew Taylor

Answer Checked By – Dawn Plyler (BugsFixing Volunteer)

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